With the rapid development of semiconductor fabrication technologies, the size of an integrated circuit chip has been reduced, but the number of chips integrated on a wafer has increased accordingly. For example, for a 4M-bit Static Random Access Memory (SRAM) chip, about 1670 chips can be fabricated in an 8-inch wafer by using the 0.13 μm fabrication process, and about 6050 chips can be fabricated in a 12-inch wafer by using the 65 nm fabrication process.
The time required for testing a SRAM chip having specific storage capacity (e.g. 4M-bit) is substantially constant. That is to say, the increase of chips integrated on a wafer may significantly increase the testing time required for performing a wafer level test. Therefore, the time required for testing a 12-inch wafer manufactured by the 65 nm fabrication process is about 3.6 times of the time required for testing an 8-inch wafer manufactured by the 0.13 μm fabrication process, thereby further increases the testing cost.
To shorten the time for testing a wafer, the technology of the prior arts uses a test machine to perform a parallel test on Multiple Devices Under Test (Multi-DUT), for example, to test 8, 16 or 32 chips under test simultaneously. However, the test capability of the parallel test is limited by the number of pins needed to be connected to each of the chips and the test pin resource of the test machine. Again, taking the 4M-bit SRAM chip as an example, if the SRAM chip has 16 data channels, then 16 data lines, 18 address lines and at least 5 control lines are needed. During the parallel test, the address lines and control lines of different chips may input the same signals, therefore the at least 23 address and control lines may share the signal channels of the test machine. However, the 16 data lines of the SRAM chip correspond to the respective memory cells of the SRAM chip, and during testing, the memory cells of different SRAM chips need to output respective readout signals to indicate whether they fail or not. Consequently, the data lines of the SRAM chips are required to be connected to the signal channels, which are independent from each other, of the test machine. Therefore, a total of at least 16*16+23=279 signal channels are needed for testing 16 chips in parallel. The cost of the test machine increases as the number of signal channels provided within the test machine increases, therefore the above mentioned parallel test method cannot effectively reduce the test cost.
Thus, there is a need for a circuit and method for testing memory devices, capable of reducing the number of required signal channels of the test machine, thereby reducing the time and cost needed for performing the wafer level test.